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? semiconductor components industries, llc, 2005 july, 2005 ? rev. 12 1 publication order number: NCV4275/d NCV4275 5.0 v, 450 ma low?drop voltage regulator the NCV4275 is an integrated low dropout regulator designed for use in harsh automotive environments. it includes wide operating temperature and input voltage ranges. the output is regulated at 5.0 v and is rated to 450 ma of output current. it also provides a number of features, including overcurrent protection, overtemperature protection and a programmable microprocessor reset. the NCV4275 is available in the dpak and d 2 pak surface mount packages. the output is stable over a wide output capacitance and esr range. features ? 5.0 v, 2% output voltage ? 450 ma output current ? very low current consumption ? active reset output ? reset low down to v q = 1.0 v ? 500 mv (max) dropout voltage ? fault protection ? +45 v peak transient voltage ? ?42 v reverse voltage ? short circuit ? thermal overload ? pb?free packages are available ? ncv prefix for automotive and other applications requiring site and control changes + ? i d q gnd ro current limit and saturation sense bandgap reference thermal shutdown reset generator figure 1. block diagram error amplifier http://onsemi.com http://onsemi.com d 2 pak 5?pin ds suffix case 936a 1 5 dpak 5?pin dt suffix case 175aa pin 1. i 2. ro tab, 3. gnd* 4. d 5. q * tab is connected to pin 3 on all packages ordering information 1 5 marking diagrams 1 1 a = assembly location wl, l = wafer lot y = year ww = work week g = lead free indicator 4275g alyww nc v4275 awlywwg see detailed ordering and shipping information in the dimensions section on page 13 of this data sheet.
NCV4275 http://onsemi.com 2 pin function description pin no. symbol description ???? ???? 1 ?????? ?????? ???????????????????????? ???????????????????????? ???? ???? ?????? ?????? ???????????????????????? ???????????????????????? ???? ???? ?????? ?????? ???????????????????????? ???????????????????????? ???? ???? ?????? ?????? ???????????????????????? ???????????????????????? ???? ???? ?????? ?????? ???????????????????????? ???????????????????????? 2.0%, 450 ma output. 22 f, esr < 5.0 to ground. maximum ratings ? rating symbol min max unit input v oltage v i ?42 45 v input peak t ransient v oltage v i ? 45 v output v oltage v q ?1.0 16 v reset output voltage v ro ?0.3 25 v reset output current i ro ?5.0 5.0 ma reset delay voltage v d ?0.3 7.0 v reset delay current i d ?2.0 2.0 ma input voltage operating range v i 5.5 42 v esd susceptibility ? human body model ?machine model ? ? 4.0 200 ? ? kv v junction t emperature t j ?40 150 c storage t emperature t stg ?55 150 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limi t values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be af fected. lead temperature soldering reflow (note 1) lead free, 60 sec?150 sec above 217 t sld ? 265 peak c leaded, 60 sec?150 sec above 183 t sld ? 240 peak c thermal characteristics characteristic test conditions (typical v alue) unit dpak 5?pin p ackage min pad board (note 2) 1 pad board (note 3) junction?to?t ab (psi?jlx, jlx ) 4.2 4.7 c/w junction?to?ambient (r ja , ja ) 100.9 46.8 c/w d 2 pak 5?pin p ackage 0.4 sq. in. spreader board (note 4) 1.2 sq. in. spreader board (note 5) junction?to?t ab (psi?jlx, jlx ) 3.8 4.0 c/w junction?to?ambient (r ja , ja ) 74.8 41.6 c/w 1. pr r ipc / jedec j?std?020c 2. 1 oz. copper, 0.26 inch 2 (168 mm 2 ) copper area, 0.062 thick fr4. 3. 1 oz. copper, 1.14 inch 2 (736 mm 2 ) copper area, 0.062 thick fr4. 4. 1 oz. copper, 0.373 inch 2 (241 mm 2 ) copper area, 0.062 thick fr4. 5. 1 oz. copper, 1.222 inch 2 (788 mm 2 ) copper area, 0.062 thick fr4. ?during the voltage range which exceeds the maximum tested voltage of i, operation is assured, but not specified. wider limits may appl y. thermal dissipation must be observed closely.
NCV4275 http://onsemi.com 3 electrical characteristics (v i = 13.5 v; ?40 c < t j < 150 c; unless otherwise noted. refer to figure 12 for conditions.) characteristic symbol test conditions min typ max unit output output v oltage v q 5.0 ma < i q < 400 ma, 6.0 v < v i < 28 v 4.9 5.0 5.1 v output v oltage v q 5.0 ma < i q < 200 ma, 6.0 v < v i < 40 v 4.9 5.0 5.1 v output current limitation i q v q = 4.5 v 450 700 ? ma quiescent current, i q = i i ? i q i q i q = 1.0 ma ? 150 200 a quiescent current, i q = i i ? i q i q i q = 250 ma ? 10 15 ma quiescent current, i q = i i ? i q i q i q = 400 ma ? 23 35 ma dropout v oltage v dr i q = 300 ma, v dr = v i ? v q , v i = 5.0 v ? 250 500 mv load regulation v q i q = 5.0 ma to 400 ma ?30 15 30 mv line regulation v q v i = 8.0 v to 32 v, i q = 5.0 ma ?15 5.0 15 mv power supply ripple rejection p srr f r = 100 hz, v r = 0.5 v pp ? 60 ? db temperature output voltage drift d vq/dt ? ? 0.5 ? mv/k reset timing d and output ro reset switching threshold v q,rt ? 4.53 4.65 4.8 v reset output low voltage v rol r ext > 5.0 k, v q > 1.0 v ? 0.2 0.4 v reset output leakage current v roh v roh = 5.0 v ? 0 10 a reset charging current i d,c v d = 1.0 v 3.0 5.5 9.0 a upper timing threshold v du ? 1.5 1.8 2.2 v lower timing threshold v dl ? 0.2 0.4 0.7 v reset delay time t rd c d = 47 nf 10 16 22 ms reset reaction time t rr c d = 47 nf ? 1.5 4.0 s thermal shutdown shutdown temperature (note 6) t sd ? 150 ? 210 c 6. guaranteed by design, not tested in production. typical performance characteristics figure 2. output stability with output capacitor esr 0.01 0.1 1 10 100 1000 output current (ma) esr ( ) minimum esr for c q = 1 f unstable esr region for c q = 1 f ? 22 f stable esr region 0 100 200 300 400 500 unstable region for c q = 1 f maximum esr for c q = 1 f ? 22 f
NCV4275 http://onsemi.com 4 figure 3. output voltage v q vs. temperature t j figure 4. output voltage v q vs. input voltage v i figure 5. output current i q vs. temperature t j figure 6. output current i q vs. input voltage v i figure 7. current consumption i q vs. output current i q figure 8. drop voltage v dr vs. output current i q 5.2 5.1 5.0 4.9 4.8 4.7 4.6 ?40 0 40 80 120 160 v q (v) t j ( c) v i = 13.5 v, r l = 25 12 10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10 v q (v) v i (v) r l = 25 t j = 25 c 1200 ?40 0 40 80 120 160 i q (ma) t j ( c) v i = 13.5 v 1000 800 600 400 200 0 1.2 1.0 0.8 0.6 0.4 0.2 0 010 20304050 i q (a) v i (v) t j = 25 c t j = 125 c 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 020406080 100 120 i q (ma) i q (ma) v i = 13.5 v, t j = 25 c 800 700 600 400 300 200 100 0 v dr (mv) 500 200 0 400 600 800 100 0 i q (ma) t j = 25 c t j = 125 c
NCV4275 http://onsemi.com 5 figure 9. current consumption i q vs. output current i q figure 10. charge current i d,c vs. temperature t j 8 7 6 4 3 2 1 0 i d,c ( a) 5 0 ?40 40 80 120 16 0 4.0 3.5 3.0 2.0 1.5 1.0 0.5 0 v du , v dl (v) 2.5 0 ?40 40 80 120 t j ( c) t j ( c) v i = 13.5 v v d = 1.0 v 160 v i = 13.5 v v du v dl figure 11. delay switching threshold v du , v dl vs. temperature t j 80 70 60 40 30 20 10 0 i q (ma) 50 100 0 200 300 400 i q (ma) 500 600 v i = 13.5 v, t j = 25 c
NCV4275 http://onsemi.com 6 application information v i c i1 1000 f c i2 100 nf c d 47 nf i i i d i d 1 4 5 2 3 gnd c q 22 f i ro i q q ro r ext 5.0 k v q v ro figure 12. test circuit NCV4275 i q circuit description the NCV4275 is an integrated low dropout regulator that provides 5.0 v, 450 ma protected output and a signal for power on reset. the regulation is provided by a pnp pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible drop out voltage and best possible temperature stability. the output current capability is 450 ma, and the base drive quiescent current is controlled to prevent over saturation when the input voltage is low or when the output is overloaded. the regulator is protected by both current limit and thermal shutdown. thermal shutdown occurs above 150 c to protect the ic during overloads and extreme ambient temperatures. the delay time for the reset output is adjustable by selection of the timing capacitor. see figure 12, test circuit, for circuit element nomenclature illustration. regulator the error amplifier compares the reference voltage to a sample of the output voltage (vq) and drives the base of a pnp series pass transistor by a buffer. the reference is a bandgap design to give it a temperature?stable output. saturation control of the pnp is a function of the load current and input voltage. over saturation of the output power device is prevented, and quiescent current in the ground pin is minimized. regulator stability considerations the input capacitors (c i1 and c i2 ) are necessary to stabilize the input impedance to avoid voltage line influences. using a resistor of approximately 1.0 in series with c i2 can stop potential oscillations caused by stray inductance and capacitance. the output capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with its almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (?25 c to ?40 c), both the capacitance and esr of the capacitor will vary considerably. the capacitor manufacturer?s data sheet usually provides this information. the value for the output capacitor c q shown in figure 12, test circuit, should work for most applications; however, it is not necessarily the optimized solution. stability is guaranteed for c q 22 f and an esr 5.0 . the range of stability versus capacitance, load current and capacitive esr is illustrated in figure 2. reset output the reset output is used as the power on indicator to the microcontroller. this signal indicates when the output voltage is suitable for reliable operation of the controller. it pulls low when the output is not considered to be ready. ro is pulled up to vq by an external resistor, typically 5.0 k in value. the input and output conditions that control the reset output and the relative timing are illustrated in figure 13, reset timing. output voltage regulation must be maintained for the delay time before the reset output signals a valid condition. the delay for the reset output is defined as the amount of time it takes the timing capacitor on the delay pin to charge from a residual voltage of 0.0 v to the upper timing threshold voltage v du of 1.8 v. the charging current for this is i d,c of 5.5 a. by using typical ic parameters with a 47 nf capacitor on the d pin, the following time delay is derived: t rd = c d v du / i d,c t rd = 47 nf (1.8 v) / 5.5 a = 15.4 ms other time delays can be obtained by changing the capacitor value.
NCV4275 http://onsemi.com 7 v i v q v d v ro reset delay time reset reaction time power?on?reset thermal shutdown voltage dip at input undervoltage secondary spike overload at output < reset reaction time t t t t v q,rt upper timing threshold v du lower timing threshold v dl dv d dt reset charge current c d figure 13. reset timing
NCV4275 http://onsemi.com 8 calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 14) is: p d(max) [v i(max) v q(min) ]i q(max) ( 1) v i(max) i q where v i(max) is the maximum input voltage, v q(min) is the minimum output voltage, i q(max) is the maximum output current for the application, i q is the quiescent current the regulator consumes at i q(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. smart regulator ? iq control features i q i i figure 14. single output regulator with key performance parameters labeled v i v q } heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (3) where r jc is the junction?to?case thermal resistance, r cs is the case?to?heatsink thermal resistance, r sa is the heatsink?to?ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heatsink data sheets of heatsink manufacturers. thermal, mounting, and heatsinking considerations are discussed in the on semiconductor application note an1040/d.
NCV4275 http://onsemi.com 9 thermal model a discussion of thermal modeling is in the on semiconduc tor web site: http://www.onsem i.com/pub/collateral/br1487?d.pdf. table 1. dpak 5?lead thermal rc network models drain copper area (1 oz thick) 168 mm 2 736 mm 2 168 mm 2 736 mm 2 (spice deck format) cauer network foster network 168 mm 2 736 mm 2 units ta u ta u units c_c1 junction gnd 1.00e?06 1.00e?06 w?s/c 1.36e?08 1.361e?08 sec c_c2 node1 gnd 1.00e?05 1.00e?05 w?s/c 7.41e?07 7.411e?07 sec c_c3 node2 gnd 6.00e?05 6.00e?05 w?s/c 1.04e?05 1.029e?05 sec c_c4 node3 gnd 1.00e?04 1.00e?04 w?s/c 3.91e?05 3.737e?05 sec c_c5 node4 gnd 4.36e?04 3.64e?04 w?s/c 1.80e?03 1.376e?03 sec c_c6 node5 gnd 6.77e?02 1.92e?02 w?s/c 3.77e?01 2.851e?02 sec c_c7 node6 gnd 1.51e?01 1.27e?01 w?s/c 3.79e+00 9.475e?01 sec c_c8 node7 gnd 4.80e?01 1.018 w?s/c 2.65e+01 1.173e+01 sec c_c9 node8 gnd 3.740 2.955 w?s/c 8.71e+01 8.59e+01 sec c_c10 node9 gnd 10.322 0.438 w?s/c sec 168 mm 2 736 mm 2 r?s r?s r_r1 junction node1 0.015 0.015 c/w 0.0123 0.0123 c/w r_r2 node1 node2 0.08 0.08 c/w 0.0585 0.0585 c/w r_r3 node2 node3 0.4 0.4 c/w 0.0304 0.0287 c/w r_r4 node3 node4 0.2 0.2 c/w 0.3997 0.3772 c/w r_r5 node4 node5 2.97519 2.6171 c/w 3.115 2.68 c/w r_r6 node5 node6 8.2971 1.6778 c/w 3.571 1.38 c/w r_r7 node6 node7 25.9805 7.4246 c/w 12.851 5.92 c/w r_r8 node7 node8 46.5192 14.9320 c/w 35.471 7.39 c/w r_r9 node8 node9 17.7808 19.2560 c/w 46.741 28.94 c/w r_r10 node9 gnd 0.1 0.1758 c/w c/w note: bold face items represent the package without the external thermal system. junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n time constants are not simple rc products. amplitudes of mathematical solution are not the resistance values. ambient (thermal ground) figure 15. grounded capacitor thermal network (?cauer? ladder) junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n each rung is exactly characterized by its rc?product time constant; amplitudes are the resistances. ambient (thermal ground) figure 16. non?grounded capacitor thermal ladder (?foster? ladder)
NCV4275 http://onsemi.com 10 table 2. d 2 pak 5?lead thermal rc network models drain copper area (1 oz thick) 241 mm 2 788 mm 2 241 mm 2 788 mm 2 (spice deck format) cauer network foster network 241 mm 2 653 mm 2 units ta u ta u units c_c1 junction gnd 1.00e?06 1.00e?06 w?s/c 1.361e?08 1.361e?08 sec c_c2 node1 gnd 1.00e?05 1.00e?05 w?s/c 7.411e?07 7.411e?07 sec c_c3 node2 gnd 6.00e?05 6.00e?05 w?s/c 1.005e?05 1.007e?05 sec c_c4 node3 gnd 1.00e?04 1.00e?04 w?s/c 3.460e?05 3.480e?05 sec c_c5 node4 gnd 2.82e?04 2.87e?04 w?s/c 7.868e?04 8.107e?04 sec c_c6 node5 gnd 5.58e?03 5.95e?03 w?s/c 7.431e?03 7.830e?03 sec c_c7 node6 gnd 4.25e?01 4.61e?01 w?s/c 2.786e+00 2.012e+00 sec c_c8 node7 gnd 9.22e?01 2.05 w?s/c 2.014e+01 2.601e+01 sec c_c9 node8 gnd 1.73 4.88 w?s/c 1.134e+02 1.218e+02 sec c_c10 node9 gnd 7.12 1.31 w?s/c sec 241 mm 2 653 mm 2 r?s r?s r_r1 junction node1 0.015 0.0150 c/w 0.0123 0.0123 c/w r_r2 node1 node2 0.08 0.0800 c/w 0.0585 0.0585 c/w r_r3 node2 node3 0.4 0.4000 c/w 0.0257 0.0260 c/w r_r4 node3 node4 0.2 0.2000 c/w 0.3413 0.3438 c/w r_r5 node4 node5 1.85638 1.8839 c/w 1.77 1.81 c/w r_r6 node5 node6 1.23672 1.2272 c/w 1.54 1.52 c/w r_r7 node6 node7 9.81541 5.3383 c/w 4.13 3.46 c/w r_r8 node7 node8 33.1868 18.9591 c/w 6.27 5.03 c/w r_r9 node8 node9 27.0263 13.3369 c/w 60.80 29.30 c/w r_r10 node9 gnd 1.13944 0.1191 c/w c/w note: bold face items represent the package without the external thermal system. the cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. the foster networks, though when sorted by time constant (as above) bear a rough correlation with the cauer networks, are really only convenient mathematical models. cauer networks can be easily implemented using circuit simulating tools, whereas foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: r(t) n i 1 r i 1?e ?t tau i
NCV4275 http://onsemi.com 11 110 150 figure 17. ja vs. copper spreader area, dpak 5?lead figure 18. ja vs. copper spreader area, d 2 pak 5?lead 100 90 80 70 60 50 40 30 200 250 300 350 400 450 500 550 600 650 700 750 copper area (mm 2 ) ja (c /w) 1 oz 2 oz 110 150 100 90 80 70 60 50 40 30 200 250 300 350 400 450 500 550 600 650 700 75 0 copper area (mm 2 ) ja (c /w) 1 oz 2 oz 100 10 1.0 0.1 0.01 time (sec) r(t) c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 cu area 167 mm 2 cu area 736 mm 2 figure 19. single?pulse heating curves, dpak 5?lead 100 10 1.0 0.1 0.01 time (sec) r(t) c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 cu area 167 mm 2 cu area 736 mm 2 sqrt(t) figure 20. single?pulse heating curves, d 2 pak 5?lead
NCV4275 http://onsemi.com 12 100 10 1.0 0.1 0.01 pulse width (sec) r ja 788 mm 2 c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 non?normalized response 50% duty cycle 20% 10% 5% 2% 1% 100 10 1.0 0.1 0.01 pulse width (sec) r ja 736 mm 2 c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 non?normalized response 50% duty cycle figure 21. duty cycle for 1? spreader boards, dpak 5?lead 20% 10% 5% 2% 1% figure 22. duty cycle for 1? spreader boards, d 2 pak 5?lead
NCV4275 http://onsemi.com 13 ordering information device package shipping ? NCV4275dtrk dpak 2500 t ape & reel NCV4275dtrkg dpak (pb?free) NCV4275ds d 2 pak 50 units/rail NCV4275dsg d 2 pak (pb?free) NCV4275dsr4 d 2 pak 800 tape & reel NCV4275dsr4g d 2 pak (pb?free) ?for information on tape and reel specifications,including part orientation and tape sizes, please refer to our tape and reel p ackaging specifications brochure, brd801 1/d.
NCV4275 http://onsemi.com 14 package dimensions d a k b r v s f l g 5 pl m 0.13 (0.005) t e c u j h ?t? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.020 0.028 0.51 0.71 e 0.018 0.023 0.46 0.58 f 0.024 0.032 0.61 0.81 g 0.180 bsc 4.56 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.045 bsc 1.14 bsc r 0.170 0.190 4.32 4.83 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 0.170 3.93 4.32 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. r1 0.185 0.210 4.70 5.33 r1 1234 5 dpak 5, center lead crop dt suffix case 175aa?01 issue a 6.4 0.252 0.8 0.031 10.6 0.417 5.8 0.228 scale 4:1 mm inches 0.34 0.013 5.36 0.217 2.2 0.086 soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d.
NCV4275 http://onsemi.com 15 package dimensions d 2 pak, 5 lead ds suffix case 936a?02 issue c 5 ref a 123 k b s h d g c e m l p n r v u terminal 6 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. tab contour optional within dimensions a and k. 4. dimensions u and v establish a minimum mounting surface for terminal 6. 5. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) maximum. dim a min max min max millimeters 0.386 0.403 9.804 10.236 inches b 0.356 0.368 9.042 9.347 c 0.170 0.180 4.318 4.572 d 0.026 0.036 0.660 0.914 e 0.045 0.055 1.143 1.397 g 0.067 bsc 1.702 bsc h 0.539 0.579 13.691 14.707 k 0.050 ref 1.270 ref l 0.000 0.010 0.000 0.254 m 0.088 0.102 2.235 2.591 n 0.018 0.026 0.457 0.660 p 0.058 0.078 1.473 1.981 r 5 ref s 0.116 ref 2.946 ref u 0.200 min 5.080 min v 0.250 min 6.350 min 45 m 0.010 (0.254) t ?t? optional chamfer 8.38 0.33 1.016 0.04 16.02 0.63 10.66 0.42 3.05 0.12 1.702 0.067 scale 3:1 mm inches soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d.
NCV4275 http://onsemi.com 16 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 NCV4275/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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